1. Technical Field
The present invention relates generally to a memory circuit for a vehicle communication system. More particularly, the invention relates to communication protocol for a dual port memory architecture which allows information exchange between two vehicle microprocessors.
2. Background and Summary of the Invention
Most dual port random access memory (RAM) devices simply allow data transfer between two microprocessors. The data is transferred by one microprocessor writing data across a shared parallel data bus that another microprocessor then reads. In effect, the dual port RAM acts as a shared memory array between the two microprocessors. This is sufficient for those applications in which each dual port RAM location is used as a standard RAM location. However, like anything else, this has its limitations. For example, certain applications require the microprocessors to know the validity of the data stored in a dual port RAM location prior to using the data. Similarly, a microprocessor which is about to write data to a dual port RAM address needs to know whether the other microprocessor has read the previously stored data in the associated location prior to overwriting and destroying data currently in that location. Naturally, the associated microprocessors could be used to keep track of the interchange of data so that it was known whether the data was current, and whether or not it had been read. This too has limitations. The problem with this additional processing is that when large amounts of data are being transferred between the microprocessors, the overhead associated with management of the dual port RAM becomes complex and time consuming. At some point, this renders microprocessor managed dual port RAM unusable in applications where speed is required.
One such application which requires speed in order to offer additional features is disclosed in U.S. patent application Ser. No. 09/839,275, entitled “Dual Port RAM with Automatic Write Indicators,” (Ward et al, assigned to the same assignee, filed Apr. 20, 2001, now abandoned). The application entitled “Dual Port RAM with Automatic Write Indicators” is directed to the sharing of data between a microprocessor used for engine management and a microprocessor used to electronically control an automatic transmission in an automobile. To thoroughly discuss how the above patent application and the present invention operate, several definitions are helpful. A “sender” refers to a microprocessor which writes data into the dual port RAM. A “receiver” refers to a microprocessor which reads data out of the dual port RAM that was placed in memory by the sender. The dual port RAM reserves two blocks of memory locations to provide communication between two microprocessors. Each block of the memory location is readable by both sender and receiver, but writable only by the sender. Specifically, a first memory location is writable only by the first microprocessor and readable by both the first and second microprocessors. A second memory location is writable only by the second microprocessor and readable by both microprocessors.
In the above mentioned patent application, status indicators or flags are used to share data between two microprocessors so as to eliminate microprocessor burdens and to provide high speed data transfer. The status indicators or flags allow a microprocessor, which reads data out of the dual port RAM, to determine whether the data to be read is current or not. It also allows a microprocessor, which writes data to the dual port RAM, to determine whether the other microprocessor has read data in the location it is about to write. By determining the validity of data, the dual port RAM prevents the overwriting and loss of data.
More specifically, when a write to a first address of the dual port RAM occurs, a write flag corresponding to the first address is placed in its associated register that is visible to both microprocessors. This write flag indicates to the receiving microprocessor that the data in the first address has been updated since the write flag was last cleared. The receiving microprocessor can then clear this flag by reading the data in the first address and clearing the flag in the associated register. Thus, the microprocessor, which reads data from the dual port RAM, knows that the stored data is current.
Similarly, the sender can also use the write flag. More particularly, the sender examines the write flag prior to writing data to a second address. If the flag has not been cleared, the sender knows that the receiver has not read the data and the data could be destroyed by overwriting. However, if the flag has been cleared, the sender knows that the data has been read and that it is safe to re-write new data to that address. Thus, a microprocessor knows whether the other microprocessor has read the data in the second address prior to overwriting and destroying data currently in the second address.
The readability of the write indicator flags by both microprocessors of the dual port RAM enables the receiver to know when new data has been written to the RAM location since it was last read (the flag is set). It also enables the sender to know when the data written to a RAM location has been utilized by the receiving side (the flag is clear) so that it can take appropriate actions. For example, if one microprocessor were to use the dual port RAM plus the other microprocessor as an expensive port expansion device, then the sending microprocessor would place data in the dual port RAM where the receiving microprocessor is expected to read out and place the value(s) on its port. The receiver would know it has new data in the dual port RAM by reading the write flag asserted by the dual port RAM state machine. The receiver would then read this data out, place the data on its own port pins, then clear the write flag. This lets the sender know that the data has been put out on the port pins. It, in effect, has confirmation that its actions have taken effect in the other microprocessor.
Although this type of communication protocol is successful for providing data transfer between two microprocessors at high speed, improvements can be made. For example, an initialization is typically performed on the dual port RAM by a sender when the system is turned on within which the dual port RAM operates. However, a receiver may retrieve data from the dual port RAM regardless of the initialization status of the dual port RAM when the sender and receiver communicate asynchronously. More particularly, the dual port RAM may not contain valid data when it is prior to initialization, or when the initialization is in progress. In such instances, the receiver may retrieve invalid data and lead to erroneous results.
What is needed is an indicator mechanism that allows to determine the validity of data communicated between two microprocessors using a dual port RAM. Accordingly, it is an object of the present invention to provide an indicator mechanism for a receiver to determine the validity of data communicated by monitoring various initialization and operational statuses of the sender. It is another object of the present invention to provide an indicator mechanism that ensures fast and accurate communication with the use of a dual port RAM.